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? isl6840, isl6841, isl6842, isl6843, isl6845 december 2008 fn9124.4 1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners ?????? pwm ??????? pwm ? isl6840, isl6841, isl6842 isl6843 isl6844 isl6845 ???? ????????? ?? ? bicmos ??? 384x ????? 60 a ???? 2mhz 20ns ???? ?? ?? isl6840 7.0v 100% isl6841 7.0v 50% isl6842 14.4v 100% isl6843 8.4v 100% isl6844 14.4v 50% isl6845 8.4v 50% ?? ? 1a mosfet ? 60 a , ?? 100 a ? ?? 30ns ? ????????? ? ???? 2mhz ? 20ns ? 1nf ? ?????????? / ??? ? ?? ? ????????? ? ??? ? pb ?? ? ? ??? ? ??? ? ? ? ??? ? ?? ? ??? ? ? isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 (8-pin soic, msop) ? comp fb rtct vre f vdd out gnd 1 2 3 4 8 cs 7 6 5 (8-pin dfn) ? 2 3 4 1 7 6 5 8 comp fb cs rtct vref vdd out gnd
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 2 ?? (c) ? ?? # isl6840ib -40 to 105 8 ld soic m8.15 isl6840ibz (see note) -40 to 105 8 ld soic (pb-free) m8.15 isl6840iu -40 to 105 8 ld msop m8.118 isl6840iuz (see note) -40 to 105 8 ld msop (pb-free) m8.118 isl6841ib -40 to 105 8 ld soic m8.15 isl6841ibz (see note) -40 to 105 8 ld soic (pb-free) m8.15 isl6841iu -40 to 105 8 ld msop m8.118 isl6841iuz (see note) -40 to 105 8 ld msop (pb-free) m8.118 isl6842ib -40 to 105 8 ld soic m8.15 isl6842ibz (see note) -40 to 105 8 ld soic (pb-free) m8.15 isl6842iu -40 to 105 8 ld msop m8.118 isl6842iuz (see note) -40 to 105 8 ld msop (pb-free) m8.118 isl6843ib -40 to 105 8 ld soic m8.15 isl6843ibz (see note) -40 to 105 8 ld soic (pb-free) m8.15 isl6843iu -40 to 105 8 ld msop m8.118 isl6843iuz (see note) -40 to 105 8 ld msop (pb-free) m8.118 isl6844ib -40 to 105 8 ld soic m8.15 isl6844ibz (see note) -40 to 105 8 ld soic (pb-free) m8.15 isl6844iu -40 to 105 8 ld msop m8.118 isl6844iuz (see note) -40 to 105 8 ld msop (pb-free) m8.118 isl6845ib -40 to 105 8 ld soic m8.15 isl6845ibz (see note) -40 to 105 8 ld soic (pb-free) m8.15 isl6845iu -40 to 105 8 ld msop m8.118 isl6845iuz (see note) -40 to 105 8 ld msop (pb-free) m8.118 isl6840irz-t* (see note) -40 to 105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6841irz-t* (see note) -40 to 105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6842irz-t (see note) -40 to 105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6843irz-t (see note) -40 to 105 8 ld 2x3 dfn (pb-free) l8.2x3 ?? (c) ? ?? # isl6844irz-t* (see note) -40 to 105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6845irz-t (see note) -40 to 105 8 ld 2x3 dfn (pb-free) l8.2x3 add -t to part number for tape and reel packaging *contact factory for availability note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination fini sh, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020 .
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 3 on v dd cs out fb rtct gnd vref pwm comparator reset dominant 2.5 v enable 8.4ma 2.6v 0.7v oscillator comparator + - uvlo comparator v ref 5.00 v + - bg + - 100mv error amplifier + - vref + - on + - s r q q comp vref uv comparator 4.65v 4.80v bg + - a=0.5 + - clock 1.1v clamp 2r r t q q isl6841/4/5 only p/n uvlo on/off -40, -41 7.0 / 6.6v -42, -44 14.3 / 8.8v -43, -45 8.4 / 7.2v a vref fault v dd ok ??
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 4 vin+ vin- retur n t1 q3 36-75v vr1 +1.8v +3.3v c1 c2 c3 r1 r3 c4 q1 r4 cr6 c5 r22 u2 cr2 cr5 cr4 c17 r21 u3 r16 c14 c13 r15 r19 r17 r18 r20 c15 c16 c12 c11 r13 c8 r10 r6 cr1 + + c21 c19 c22 c20 + + c6 isl684x v dd rtct cs fb out comp vre f gnd r26 r27 u4 ? : 48v ? ?
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 5 ?? supply voltage, v dd ------------------------------gnd-0.3v to +20v out------------------------------------------ gnd - 0.3v to v dd + 0.3v signal pi ns-------------------------------------------gnd-0.3v to 6.0v peak gate current --------------------------------------------------- 1a esd classification human body model (per mil-std-883 method 3015.7) ----------- 2000v charged device model (per eos/esd ds5.3, 4/14/93) ------------ 1000v supply voltage range (typical) is l6840/1 --------------------------------------------- 7. 5v-14vdc isl6843/5 -------------------------------------------------- 9-16vdc is l6842/4 ---------------------------------------------- 15v -18vdc temperature range isl684xlx------------------------------------------- -40 o c to 105 o c ? thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) dfn package (note 2) ---------------------77 6 soic package------------------------------- 100 n/a msop package------------------------------130 n/a maximum junction temperature ----------------------- - 55 o c to 150 o c maximum storage te mperature range -------------- - 65 o c to 150 o c maximum lead temperatur e (solderi ng 10s) ------------------ 300 o c (soic ? lead tips only) caution: stress above those listed in ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. notes: 1) ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. 2) for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3) all voltages are to be measured with res pect to gnd, unless otherwise specified. electrical specifications recommended operating conditions, unless otherwise noted. refer to block diagram and typical application schematic. v dd = 15v (note 7), r t = 10k , c t = 3.3nf, t a = -40 o c to 105 o c (note 4), typical values are at t a = 25 o c. parameter test conditions min typ max units undervoltage lockout start threshold (isl6840, isl6841) 6.5 7.0 7.5 v start threshold (isl6843, isl6845) 7.8 8.4 9.0 v start threshold (isl6842, isl6844) 13.3 14.3 15.3 v stop threshold (isl6840, isl6841) 6.1 6.6 6.9 v stop threshold (isl6843, isl6845) 6.7 7.2 7.7 stop threshold (isl6842, isl6844) 8.0 8.8 9.6 v hysteresis (isl6840, isl6841) - 0.4 - v hysteresis (isl6843, isl6845) - 0.8 - v hysteresis (isl6842, isl6844) - 5.4 - v start-up current, i dd v dd < start threshold - 60 100 a operating current, i dd (note 5) - 3.3 4.0 ma operating supply current, i d includes 1nf gate loading - 4.1 - ma reference voltage overall accuracy over line (v dd = 12v to 18v), load, temp 4.925 5.000 5.050 v long term stability t a = 125 o c, 1000 hours (note 6) - 5 - mv fault voltage 4.40 4.65 4.85 v vref good voltage 4.60 4.80 vref- 0.05 v hysteresis 50 165 250 mv current limit, sourcing -20 - - ma Z
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 6 current limit, sinking 5 - - ma electrical specifications recommended operating conditions, unless otherwise noted. refer to block diagram and typical application schematic. v dd = 15v (note 6), r t = 10k , c t = 3.3nf, t a = -40 o c to 105 o c (note 3), typical values are at t a = 25 o c. (continued) parameter test conditions min typ max units current sense input bias current v cs = 1v -1.0 - 1 a cs offset voltage v cs = 0v (note 6) 95 100 105 mv comp to pwm comparator offset voltage v cs = 0v (note 6) 0.80 1.15 1.30 v input signal, maximum 0.91 0.97 1.03 v gain, a cs = dv comp /dv cs 0 < v cs < 910mv, v fb = 0v (note 6) 2.5 3 3.5 v/v cs to out delay (note 6) - 25 40 ns error amplifier open loop voltage gain (note 6) 60 90 - db unity gain bandwidth (note 6) 3.5 5 - mhz reference voltage v fb = v comp 2.475 2.500 2.525 v fb input bias current v fb = 0 -1.0 -0.2 1.0 a comp sink current v comp = 1.5v, v fb = 2.7v 1.0 - - ma comp source current v comp = 1.5v, v fb = 2.3v -0.4 - - ma comp voh v fb = 2.3v 4.80 - vref v comp vol v fb = 2.7v 0.4 - 1.0 v psrr frequency = 120hz, v dd = 12v to 18v (note 6) 60 80 - db oscillator frequency accuracy initial, t j = 25 o c 49 52 55 khz frequency variation with v dd t = 25 o c (f 18v - f 12v )/f 12v - 0.2 1.0 % temperature stability (note 6) - - 5 % amplitude, peak to peak - 1.9 - v rtct discharge voltage - 0.7 - v discharge current rtct = 2.0v 7.2 8.4 9.5 ma output gate voh v dd - out, i out = -200ma - 1.0 2.0 v gate vol out - gnd, i out = 200ma - 1.0 2.0 v peak output current c out = 1nf (note 6) - 1.0 - a rise time c out = 1nf (note 6) - 20 40 ns fall time c out = 1nf (note 6) - 20 40 ns pwm isl6840, isl6842, isl6843 94 96 - % maximum duty cycle isl6841, isl6844, isl6845 47 48 - % Z
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 7 electrical specifications recommended operating conditions, unless otherwise noted. refer to block diagram and typical application schematic. v dd = 15v (note 6), r t = 10k , c t = 3.3nf, t a = -40 o c to 105 o c (note 3), typical values are at t a = 25 o c. (continued) isl6840, isl6842, isl6843 - - 0 % minimum duty cycle isl6841, isl6844, isl6845 - - 0 % notes: 4. specifications at -40 o c are guaranteed by design, not production tested. 5. this is the v dd current consumed when the device is active but not switching. does not include gate drive current. 6. guaranteed by design, not 100% tested in production. 7. adjust v dd above the start threshold and then lower to 15v. 1.02 1.01 1 0.99 0.98 0.97 -40 -10 20 50 80 11 0 temperat ure ( c ) normalized frequency temperatur e ( o c ) normalized v ref 1.001 1 0.999 0.998 0.997 0.996 0.995 -40 -25 -10 5 20 35 50 65 80 95 11 0 figure 1. frequency vs temperature figure 2. reference voltage vs temperature temperature ( c ) normaliz ed ea reference 1.002 1 0.998 0.996 0.994 -40 -25 -10 5 20 35 50 65 80 95 11 0 1-10 3 100 10 1 10 20 30 40 50 60 70 80 90 100 rt ( k figure 3. ea reference vs temperature figure 4. rtct vs frequency ? Z
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 8 ?? r tct ???? (r t ) v ref ?? (c t ) gnd ??? ???????? 2.0mhz ?? ?? t c ) ??? t d ?? f ? ?? d max ? : t t c c r 583 . 0 t ? ? (eq. 1) ) 4 . 2 r 0083 . 0 3 . 4 r 0083 . 0 ln( c r t t t t t d ? ? ? ? ? ? ? (eq. 2) ) t t /( 1 f d c + = (eq. 3) f t max d c ? = (eq. 4) ???????? 4 ?? . comp comp ?? pwm ?? ???? comp fb ?? fb ?????? ? ????? cs pwm ?? ???? ? 0 1.0v 100mv ??? gnd ?????? out ???? 1.0a ? mosfet ? vdd uvlo ??? ?? vdd vdd ?????? out ? idd ????? ??? f mosfet ?? qg ? 1?? f q i g out ? = (eq. 5) ???????? v dd gnd ? vref 5.00v ???? +1.0/-1.5% ? ???? 0.1 f 3.3 f ? gnd ? ? ?? isl684x ?? pwms ????? ????????? ?? , isl684x ??? ? isl684x ????? 2mhz ? rtct ? vref ? gnd ?? ( ??l???? 4 ) ????? f , ?? comp so ft s tart vre f comp gnd isl684x figure 5. soft start ? isl684x ? 1a ?????^ ic, ??? ic (out ) mosfet T?g fet ????
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 9 2 ???? 50% ? , 2?? , ??? ????? 2 , ?s 10% ???? ?? ??? 50% ? , 2?? 2????? 2??????????? ? time cs signal (v) down slope current sense signal figure 6. current sense downslope ??A cs ?: slop e compensation vref rt ct cs isl684x figure 7. slope compensation ? vref 4.65v ??? out ??? vref 4.80v ? , ?? , out ? ???????? ????????? di/dt vdd ????? ? ( gnd )
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 10 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating pl ane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are for reference only m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n 8 8 7 0 o 8 o 0 o 8 o - rev.0 12/93
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 11 mini small outline plastic packages (msop) l 0.25 (0.010) l1 r1 r 4x 4x gauge pl ane se ati ng plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a bc seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side v iew b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a notes: 1. these package dimensions are within allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. dimension ?d? does not incl ude mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions and are measured at datum plane.interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum material condition. minimu m space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums -a- and -b- to be determined at datum plane -h-. 11. controlling dimension: millimeter. converted inch dimensions are for reference only. m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n 8 8 7 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 0 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev.2 01/03
isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resul t from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com 12 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a mc n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3 8 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d2.00 bsc- d2 1.50 1.65 1.75 7,8 e3.00 bsc- e2 1.65 1.80 1.90 7,8 e0.50 bsc- k0.20 - - - l 0.30 0.40 0.50 8 n 8 2 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389.

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